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| 1 www.semtech.com power management sc2434 triphase current mode controller with power good may 18, 2005 description features the sc2434, a tri-phase, current mode controller is designed to work with semtech smart synchronous drivers, such as the sc1205, sc1206, and sc1207 to provide the dc/dc converter solution for the most demanding microprocessor applications. input current sensing is used to guarantee precision phase to phase current matching using a single sense resistor on the input power line. this topology reduces the power loss and complexity associated with output current sense methods. multi phase operation allows significant reduction in input/output ripple while enhancing transient response. two or three phase operation is selectable. the dac step size and range are program- mable with external components thus allowing compliance with new and emerging vid ranges. a novel approach implements active droop to minimize output capacitors during load transients. ! 12v input ! input sensing current mode control ! selectable 2 or 3 phase operation ! precision, pulse by pulse phase current matching ! active drooping allows for best transient response ! programmable internal oscillator to 1.5 mhz ! programmable dac step size/offset allows compli- ance with vrm9.0 and vrm9.2 ! vid 11111 inhibit (no cpu) ! externally programmable soft-start ! 0% minimum duty cycle improves transient response ! cycle by cycle current limiting plus hiccup ! power good signal ! intel pentium-4 microprocessors ! ! ! ! ! high performance desktop systems typical application circuit applications +12v c17 1uf d1 1n4148 +5v r2 2r2 r9 2r2 l4 600nh +5v_atx c6 4.7uf + c21 1500uf/6.3v d6 1n4148 + c2 2200uf/16v vid0 c24 1uf r_os 46.4k + c26 1500uf/6.3v c23 2.2nf + c7 1500uf/6.3v d3 1n4148 c16 4.7uf m4 + c10 1500uf/6.3v u1 sc1205 1 2 3 4 5 6 7 8 drn tg bst co en vs bg pgnd c5 4.7uf m5 r4 1r + c18 1500uf/6.3v r29 100 vccvid_pwrgd(open collector input) + c32 1500uf/6.3v +12v vout c35 1uf c4 1uf c9 1nf m6 differential pair r_comp 75k c15 1uf +12v c22 1nf l1 600nh u2 sc2434 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vid4 vid3 vid2 vid1 vid0 pgin errout pgout fb oscref dacref oc+ oc- agnd pc out3 out2 out1 bgout vcc d2 1n4148 r10 1r r5 20 d5 1n4148 c34 2.2nf + c28 1500uf/6.3v r15 1k r_osc 31.6k c27 1uf l2 600nh vid4 m3 r17 1 sm/r_1206 differential pair m2 r14 2r2 r6 1 sm/r_1206 c76 0.33uf c75 0.33uf c11 2.2nf u3 sc1205 1 2 3 4 5 6 7 8 drn tg bst co en vs bg pgnd c33 1nf + c30 1500uf/6.3v + c14 1500uf/6.3v r1 3m r16 1r m1 + c1 2200uf/16v v_pull_up + c19 1500uf/6.3v r_fb 10k + c20 1500uf/6.3v c77 0.33uf r_drp 187k d4 1n4148 r3 2r2 c31 470pf r8 no pop + c3 2200uf/16v vid3 r13 5.1k + c25 1500uf/6.3v +5v c12 1uf agnd c13 10nf c_comp 18pf +12v_atx c29 100nf vid1 c8 1uf pwr_good r19 750 vid2 u4 sc1205 1 2 3 4 5 6 7 8 drn tg bst co en vs bg pgnd pgnd r_dac 37.4k l3 600nh r11 1 sm/r_1206 r20 1k
2 ? 2005 semtech corp. www.semtech.com preliminary power management sc2434 r e t e m a r a pl o b m y sm u m i x a ms t i n u d n g o t e g a t l o v l i a r c d t u p n iv n i 8 1v e g n a r e r u t a r e p m e t t n e i b m at a 0 7 o t 0c e r u t a r e p m e t n o i t c n u jt j 5 2 1 o t 0c e s a c o t n o i t c n u j e c n a t s i s e r l a m r e h t c j 0 2w / c t n e i b m a o t n o i t c n u j e c n a t s i s e r l a m r e h t a j 0 6w / c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3c r e t e m a r a ps n o i t i d n o cn i mp y tx a mt i n u y l p p u s _ p i h c e g a t l o v y l p p u s c i 0 12 14 1v t n e r r u c y l p p u s c iv c c =v 0 . 2 10 15 1a m n o i t c e s e c n e r e f e r t u p t u o p a g d n a bc g b f n 7 . 4 =5 . 1v e c n a d e p m i e c r u o s 6k ? n o i t c e j e r y l p p u sv c c v 0 . 4 1 ~ v 0 . 0 1 =5 .v / v m p e t s d i vr b f 0 1 =k ? r , c a d 4 . 7 3 =k ? 5 2v m y t i l i b a t s e r u t a r e p m e tt < c 0 b m a c 0 7 <5 . 0% y c a r u c c a e g a t l o vt < c 0 b m a c 0 7 <8 . 0 -8 . 0 +% n o i t c e s r o t a l l i c s o e g n a r y c n e u q e r f 0 0 30 0 5 1z h k y c a r u c c a y c n e u q e r fv n i v 0 . 2 1 =5 7 60 5 75 2 8z h k y t i l i b a t s e r u t a r e p m e tt < c 0 b m a c 0 7 <5 % r e i f i l p m a r o r r e e g a t l o v e g a t l o v t e s f f o t u p n i 5 v m t n e r r u c t e s f f o t u p n i 1 . 0a n i a g p o o l n e p ov < v 1 t u o r r e v 4 <0 9b d r r s pv c c v 4 1 - 9 =0 8b d t n e r r u c k n i s t u p t u ov t u o r r e v 1 =5 . 2a m t n e r r u c e c r u o s t u p t u ov t u o r r e v 4 =2a m h t d i w d n a b n i a g y t i n ui o a 0 0 1 <6 . 1z h m e t a r w e l si o a 0 0 1 <0 1/ vs unless specified: v cc = +12v, t amb = 25c, r dac = 37.4k ? , r osc = 28.5k ? . see typical application circuit exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied. absolute maximum ratings electrical characteristics 3 ? 2005 semtech corp. www.semtech.com power management sc2434 r e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a mt i n u r e i f i l p m a e s n e s t n e r r u c n i a g r e i f i l p m av ( c o v - - + c o v m 0 2 1 < )9 . 8 13 . 9 17 . 9 1v / v t u p n i , e g a t l o v t e s f f o t u p n i d e r r e f e r v ( c o --v + c o )< 2 1v m 04v m r r m cv m c i =9~ v 4 1@c d0 8b d r r s pv c c =9~ v 4 1@c d0 8b d e g n a r e d o m n o m m o c t u p n i v c c 3 . 0 v t n e r r u c / l a n g i s l a i t n e r e f f i d x a m d l o h s e r h t t i m i l v - c o -v + c o 0 2 1v m y a l e d t i m i l - i, 1 t u o o t n o i t a v i t c a t i m i l t n e r r u c f f o g n i h c t i w s 3 t u o & 2 t u o 0 6s n o l v u c c v d l o h s e r h t p u - p m a r 5 . 7v d l o h s e r h t n w o d - p m a r 5 2 . 7v ) 3 t u o , 2 t u o , 1 t u o ( s t u p t u o e s a h p r e p e l c y c y t u d x a mf c s o g n i t a o l f n i p c p , z h k 0 0 5 =1 3% f c s o d e d n u o r g n i p c p , z h k 0 0 5 =7 4% e g a t l o v t u p t u or l k 0 1 = ? h g i h ,5 . 2v r l k 0 1 = ? w o l ,8 . 0 r l k 0 0 1 = ? h g i h ,3 . 3v r l k 0 0 1 = ? w o l ,2 . 0 t u p n i c i g o l d l o h s e r h t c i g o l d i v ) 2 ( ) 1 ( 8 . 02v e c n a d e p m i c i g o l d i vv 5 . 2 = p u - l l u p l a n r e t n i5 2k ? l o r t n o c e s a h p d l o h s e r h t c i g o l ) 2 ( 8 . 02v p u - l l u p l a n r e t n it i u c r i c n e p o n i p c p5 . 2v e c n a d e p m i p u - l l u p l a n r e t n i 5 2k ? l a n g i s d o o g r e w o p t n e r r u c e g a k a e l f f oh g i h c i g o l = d o o g r w p2a t n e r r u c k n i s x a m d o o g r e w o pd o o g r w p 5 ? 2005 semtech corp. www.semtech.com power management sc2434 block diagram applications information- output voltage e g a t l o v t u p t u o t . ) g n i t a o l f r o ( h g i h = 1 ; d n g = 0 : d e i f i c e p s s s e l n u a v , c 5 2 = c c . n o i t a r e p o e s a h p - 3 , v 2 1 = v e r o c c c 4 d i v3 d i v2 d i v1 d i v0 d i v) c d v ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 f f o t u p t u o 1 . 1 5 2 1 . 1 5 1 . 1 5 7 1 . 1 2 . 1 5 2 2 . 1 5 2 . 1 5 7 2 . 1 3 . 1 5 2 3 . 1 5 3 . 1 5 7 3 . 1 4 . 1 5 2 4 . 1 5 4 . 1 5 7 4 . 1 5 . 1 5 2 5 . 1 5 5 . 1 5 7 5 . 1 6 . 1 5 2 6 . 1 5 6 . 1 5 7 6 . 1 7 . 1 5 2 7 . 1 5 7 . 1 5 7 7 . 1 8 . 1 5 2 8 . 1 5 8 . 1 6 ? 2005 semtech corp. www.semtech.com preliminary power management sc2434 theory of operation the simplified voltage regulator (vr) based on sc2434 is depicted in fig. 1. the key timing chart is also shown in the same picture. the 12v input power passes through the input filter establishing the input power rail. the cur- rent sensing resistor located at positive input rail moni- tors the top fet currents of all the phases. an internal differential amplifier amplifies the voltage across the current sensing resistor. the output of the current am- plifier and an internally generated saw tooth ramp signal are added together to be the pwm carrier signal. this signal meets the output of the error amplifier at the pulse width modulator (pwm). the output of the pwm is then divided into three phases alternately to be the inputs of the synchronous drivers. feedback and regulation the feedback circuitry reads the regulator output volt- age and compares it with an accurately trimmed bandgap voltage reference, which is 1.5v with less then 0.8% tol- erance. the compensation network allows optimization of the control-loop for system stability and fast transient responses. applications information flexible vid the vid circuitry reads the 5 bit digital command and converts it into a current flowing into the inverting input pin of the error amplifier. the output current of the dac produces a voltage offset on the feedback resistor, r fb (see fig. 1), which changes the set point of the converter output voltage for different vid combinations. active voltage positioning by programming the gain of the error amplifier, one can easily and accurately implement adaptive output voltage positioning. this is equivalent to programming the vr output impedance in an active manner. the advantage of allowing the vr certain output impedance (typically 1~3 mohm) is that one can use a minimum amount of high quality output bulk capacitors to meet the voltage regulation requirement. hence, the cost and the size of the vr solution can be significantly reduced. sc2434 fig.1 - the simplified voltage regulator based on sc2434. 7 ? phase current balance one of the fundamental challenges for multi-phase solu- tions is to balance the phase currents to achieve the best possible electrical and thermal performance. it is quite easy to use the sc2434 control topology to achieve very good phase current balance. since the current of all the phases passes through the same current sensing compo- nent and the same current current of all the phases are well balanced on pulse by pulse basis. this control results in small and even output voltage ripple and evenly distrib- uted thermal load. additional advantages of using input current mode are less sensing circuitry, less ic pins, and less power loss on the sensing resistor comparing sensing inductor current on the output side. fig. 2 shows the wave- form of inductor currents under heavy load conditions, which clearly demonstrates the excellent performance of sc2434 on balancing the phase current. applications information (cont.) voltage. fig. 3 shows the measured waveforms of power up and power down. fig. 3 - shows the measured waveforms of power up and power down. over current protection (ocp) when sensed current signal across the differential input of the current amplifier exceeds 120mv typical value, ocp circuitry will pull down the error amplifier output voltage and also discharge the soft start capacitor. the pull down of the error amplifier will not be released until the soft capacitor is discharged bellow 0.3v. at this point, the pwm outputs are reactivated and the soft start capacitor begins to charge up again through the internal 6 kohm resistor. the vr will try to bring up the output voltage until the over load or short circuit condition is removed. the hiccup mode ocp can significantly reduce the average out- put current under overload conditions. the hiccup timing is controlled by the soft start time constant. please also notice that the ocp threshold has less than 10% toler- ance, hence, the onset of the ocp is quite accurate. the advantage is that the vr designer does not need to re- serve big thermal headroom to deal with the worst-case operation when load is over 100% but the ocp has yet not been triggered. an rc filter is needed to filter out the leading edge voltage spike across the current sensing re- sistor to prevent false triggering of the ocp. the time con- stant should be around 200ns (please see application schematic). power good sc2434 features a power good input and an open collec- tor power good output. the vr output voltage is scaled down through a resistive divider and this signal is fed into pgin (power good input) pin. the scaled vr output volt- age has to be bigger than 0.8v otherwise the power good output pin is pulled down. a 5 kohm pull-up resistor and a 0.1uf capacitor to ground are recommended to prevent false trigger during logic transition. fig. 2 - measured inductor currents of sc2434 3-phase vr under heavy load condition. under voltage lockout (uvlo) during power up, when uvlo circuitry detects the chip supply (vcc) be bigger than 7.5v (typical value with proper hysteresis), the bandgap voltage reference starts to charge the external soft start capacitor through a 6 kohm inter- nal resistor. when soft start capacitor voltage reaches 0.5v, the output voltage starts to build up which follows the exponential voltage profile of the soft start capacitor. the soft start process ensures that the output voltage will have no over shoot. during power down, uvlo will dis- charge the soft start capacitor to shut of the pwm. the load will absorb the energy in the output filter and no reso- nance will occur. hence, the cpu will not see any negative output volta g e output volta g e input volta g e input volta g e 8 ? 2005 semtech corp. www.semtech.com preliminary power management sc2434 applications information (cont.) program the controller please refer to fig. 1 and the application schematics in this data sheet for the discussion. the resistor from pin 10 to ground, r osc , programs the switching frequency. the resistor from pin 11 to ground, r dac , sets the dac current step size. the resistors, r fb , r os , and r drp set the dac step size, the output voltage set point, and the droop, respectively. mathcad programs are available to calculate the required parameters upon request. programming the switching frequency the oscillator frequency can be selected first by setting the value of r osc as given below: r osc 28.5 k ? . . . . the per phase switching frequency is 1/3 of the oscilla- tor frequency in three-phase mode. it is recommended that per phase switching frequency is 200~300khz for good trade off of efficiency vs. transient responses. programming the dac step size the sc2434 allows programming of the output voltage and the dac step size by selecting external resistors. the lsb of the dac current is given by: where v bg is the trimmed voltage reference (v bg = 1.5v) and r dac is the resistor from pin 11 to ground. for the given vid step size (25mv for vrm9.0 and vrm9.2 speci- fications), the feedback resistor can be calculated accord- ing to the lsb of dac current: the above two equations are for choosing r dac and r fb simultaneously. the advantage of this method is that new vid step size can be accommodated by modifying external components while maintaining the required precision. choose current sensing resistor according to the threshold of ocp the sc2434 controller has an over current protection (ocp) threshold of 120mv. the normal practice is to let the peak voltage across the sensing resistor corresponding to full-load operation be 75% of the given ocp threshold: r drp r fb r sense . . ? ? . where i peak is the peak current of the output inductor. since the choice of sensing resistor values are limited, typically 3 mohm, 4 mohm, or 5 mohm, it is recommended to choose the sensing resistor with a bigger value than that was cal- culated, and to use a resistive divider to get the equiva- lent r sense value. the two attenuation resistors should have value of 20 ohm in parallel. a filter capacitor of 10nf is also needed to be across the oc+ and oc- pins of the controller ic. please refer the application circuit sche- matic. programming the dynamic (active) droop to optimize transient responses, the sc2434 actively regu- lates output voltage as a function of output current. at zero current the output is positioned to the upper limit of the regulation window. as the load increases, the output ?droops? towards the lower limit. this makes optimum use of the output voltage error band, yielding minimum output capacitor size and cost. the droop is adjusted by setting the dc gain of the error amplifier. this is done by choosing the resistor from the errout pin to the fb pin (r drp ) of the controller. while the optimum value of r drp may be derived experimentally, the following equation can provide the first order calcula- tion for given droop slope: where r sense is the current sensing resistance after taken into account of attenuation, and g ca is the gain of the current amplifier while n phase is number of phases being used. any output interconnection impedance not within the feed- back loop can contribute to additional drooping. this ef- fect has to be taken into account. usually, when testing the regulation at different cpu pins, the results may vary slightly by same token. it is important to use surface mount current sensing resis- tor to minimize the parasitic inductance for accurate cor- relation between the above equation and the test results. this is because the inductive contribution, which may also r sense 75% " 120m v i peak 9 ? programming the dc level of the output voltage kirchoff?s current law can be applied to the error amplifier?s inverting input (see fig. 1) to calculate r os , the dc level setting resistor. for given output voltage set point and vid setting, the resistance can be calculated by: applications information (cont.) h p_ccm sr , . . . . . . . . . control loop compensation the current mode control yields a power supply easy to compensate because the power stage has first order (single pole) behavior. the sc2434 provides internal slope compensation to avoid sub harmonic oscillation of the current loop. the added ramp signal has 300mv peak-to- peak amplitude and the ramp frequency is as same as the oscillator frequency. as depicted in fig. 4, the gain for the voltage feedback loop can be expressed as a product of the power stage gain and the compensator gain: loop s r , , . 0 - + err_amp ver ror lo op g ain copam ccomp rcomp -1 ccomp 1/(r*c) rdrp po wer stage rdrp/r fb vin/( vr*n ph as e) -1 power st age c o mp en sa tor 1/( e src ) pol e fsw/2 zero 0db fsw/2 -2 -2 1/( r*c ) vo ut where g pwm is the low frequency gain of the power stage. the power stage has an esr zero, a dominant pole at low frequency, and a pair of complex pole located at one half of the switching frequency. the parameter used here are defined as below: c = output bulk capacitance r = load resistance r c = esr of output bulk capacitor f sw = switching frequency the pwm gain is defined as: r os v bg v set v bg r fb v eo v bg r drp n dac_step i dac_lsb . ! n r phase sense g ca 10 ? h c s () r drp r fb 1 s z 1 s p1 1 s p2 . . 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 40 20 0 20 40 loop-gain (db) mag_loop i r , () 0 f i 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 180 90 0 90 180 loopgain (degree) p hase_loop i r , () f i 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 40 20 0 20 40 loop-gain (db) mag_loop i r , () 0 f i 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 40 20 0 20 40 loop-gain (db) mag_loop i r , () 0 f i 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 180 90 0 90 180 loopgain (degree) p hase_loop i r , () f i 11 ? 2005 semtech corp. www.semtech.com power management sc2434 pcb layout consideration good layout is necessary for successful implementation of the sc2434 based 3 tri-phase topology. there are few general rules: reserve enough pcb space for the power supply (1.2~1.5 square inch for every 10a of load current); place enough high frequency ceramic capacitors inside and around the cpu socket (please follow cpu manufacture?s decoupling guideline); place bulk output capacitors around the cpu socket as uniformly as possible. the connection copper between these capacitors and the cpu socket must be short and wide to minimize inductance and resistance; always place the high power parts first; always use a ground plane or ground planes; always try to minimize the stray inductance of the high pulsating current loop which is formed by input capacitors and the mosfet half-bridges. the following layout guideline gives details on how to achieve a good layout: input filter should contain mixed electrolytic capacitors and mlc capacitors. for every 20a of load current, use about 10uf of mlc caps. put mlc caps close to current sensing resistor; use surface mount current sensing resistor (typically 3~5 mohm in surface mount package with low temperature coefficient and low package inductance, typically less than 0.3nh); try to minimize the stray inductance from the current sensing resistor to the drains of the top fets by using wide trace (>0.5? wide and no more than 3? long). this trace can run on inner1 layer, for example, if the inner2 layer is the ground plane, assuming the fets are on the top layer. this arrangement forms so called strip line structure for the pulsating power current, which yields least amount of stray inductance. the concept is depicted in fig. 7; keep the layout as electrically symmetrical as possible, as shown in fig. 8, to avoid very uneven stray inductance from the sensing resistor to the drains of the top fets; use a pair of closely paralleled traces to pick up the sensing voltage across the sensing resistor. the sensing traces server as differential input to the oc+ and oc- pins of the sc2434 controller. these traces should run on a routing layer (e.g., bottom layer for 4 layer pcb case) to avoid picking up strong ac magnetic field due to power current flow. in this case, the differential sensing traces are shielded by the ground layer. the filter cap across the oc+ and oc- pins should be placed as close as possible to the controller. pay close attention that never allow power current flowing on or running close by the sensing traces. please see fig. 8; separate power ground from analog ground to prevent power current from running over the analog ground plane. the sc2434 controller should be placed on the quite analog ground area. the analog ground should be single- point connected to the pgnd near the output capacitor or the cpu socket to provide best possible ground sense. refer to the application schematics for those components should be connected directly to the agnd (vcc decoupling caps, cap on bgout pin, resistors on oscref pin, dacref pin, fb pin, and pgin pin). fig. 7 - use mlc capacitors and strip line structure to minimize the stray inductance for the switching current loop. top fet bot fet d sd s mlc via via rsense ground plane applications information (cont.) 12 ? 2005 semtech corp. www.semtech.com preliminary power management sc2434 fig. 8 - layout concept for input current sensing: (a) use mlc input capacitors; (b) minimize inductance; (c) keep electrical symmetry; and (d) use differential sensing traces. a reference design example for intel pentium iv processor brief specifications of this design are listed below: ? v in =12v ? v out =1.725v +/- 25mv at 0a load ? v out droop slope is 1.5 mohm ? v out tolerance is +/-25mv for all load conditions ? i out = 60a max ? vid [4:0] = 00100 the schematic is shown on the cover page of this data sheet. applications information (cont.) 13 ? 2005 semtech corp. www.semtech.com power management sc2434 bill of materials - reference design m e t i. y t qe c n e r e f e re u l a v. o n t r a p / n o i t p i r c s e de g a k c a pr o d n e v 11 p m o c _ cf p 7 4t a x x k 0 7 4 y 3 0 6 j v , c c l m , r 7 x , v 0 13 0 6 0y a h s i v 211 cf u 3 3 . 0t a x x k 4 3 3 y 5 0 8 j v , c c l m , r 7 x , v 5 25 0 8 0y a h s i v 33 4 c , 3 c , 2 cf u 0 0 2 2p a c . c e l e . l a v 5 1/ 0 0 4 . d / l y c p c 4 3 0 . / 0 0 2 . s l o y n a s 48 , 3 1 c , 9 c , 5 c , 8 1 c , 5 1 c 8 3 c , 0 3 c , 6 2 c f u 1d n - t c 9 4 8 1 c c p , c c l m , v 5 y , v 6 15 0 8 0c i n o s a n a p 53 6 1 c , 7 c , 6 cf u 7 . 4d n - t c 0 0 9 1 c c p , c c l m , v 5 y , v 6 16 0 2 1c i n o s a n a p 62 1, 4 1 c , 0 1 c , 8 c , 2 2 c , 0 2 c , 9 1 c , 8 2 c , 7 2 c , 3 2 c 5 3 c , 3 3 c , 1 3 c f u 0 0 5 1z b m n o c u b y r p a c . l a v 3 . 6/ 5 2 3 . d / l y c p c 4 3 0 . / 5 2 1 . s l n o c i b u r 73 6 3 c , 4 2 c , 1 1 cf n 1t a x x k 2 0 1 y 3 0 6 j v , c c l m , r 7 x , v 6 13 0 6 0y a h s i v 83 7 3 c , 5 2 c , 2 1 cf n 2 . 2t a x x k 2 2 2 y 5 0 8 j v , c c l m , r 7 x , v 0 55 0 8 0y a h s i v 92 9 2 c , 7 1 cf u 3 3 . 0t a x x k 4 3 3 y 3 0 8 j v , c c l m , r 7 x , v 5 25 0 8 0y a h s i v 0 111 2 cf n 0 1t a x x k 3 0 1 y 3 0 6 j v , c c l m , r 7 x , v 0 13 0 6 0y a h s i v 1 112 3 cf n 0 0 1t a x x k 4 0 1 y 3 0 6 j v , c c l m , r 7 x , v 6 13 0 6 0y a h s i v 2 114 3 cf p 0 7 4t a x x k 1 7 4 y 3 0 6 j v , c c l m , r 7 x , v 0 13 0 6 0y a h s i v 3 16 , 4 d , 3 d , 2 d , 1 d 6 d , 5 d a 3d n - t c s m 8 4 1 4 l d y l t t o h c s m s v 0 3c a 3 1 2 o dy e k - i g i d 4 14 4 l , 3 l , 2 l , 1 lh n 8 3 68 3 6 - 5 0 3 1 f i t t r o t c u d n i , a 0 2 , h n 8 3 60 1 . / 0 0 4 w / 0 0 5 l / n io c l a f 5 13 5 m , 3 m , 1 ml b 6 3 0 6 b d ft e f s o mb a 3 6 2 - o td l i h c r i a f 6 12 4 m , 2 ml 5 4 0 7 b d ft e f s o mb a 3 6 2 - o td l i h c r i a f 7 116 ml 5 4 0 7 p d ft e f s o mb a 3 6 2 - o td l i h c r i a f 8 11 p m o c _ rk 4 . 9 2f 2 4 9 2 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 9 11 c a d _ rk 4 . 7 3f 2 4 7 3 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 0 21 p r d _ rk 7 8 1f 3 7 8 1 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 1 21 b f _ rk 0 . 0 1f 2 0 0 1 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 2 21 s o _ rk 4 . 6 4f 2 4 6 4 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 3 21 c s o _ rk 6 . 1 3f 2 6 1 3 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 4 211 rm 3w 0 2 5 7 l r % 1 r g n i s n e s m s2 1 5 2c e t n y c 5 24 3 1 r , 8 r , 5 r , 2 r2 r 2f 2 r 2 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 6 213 r0 2f 0 r 0 2 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 7 23 5 1 r , 0 1 r , 4 r0 r 1f 0 r 1 3 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 8 216 r0 0 1f 0 0 0 1 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 9 23 6 1 r , 1 1 r , 7 r0 r 1f 0 r 1 6 0 2 1 w c r c % 1 m s6 0 2 1y a h s i v 14 ? 2005 semtech corp. www.semtech.com preliminary power management sc2434 m e t i. y t qe c n e r e f e re u l a v. o n t r a p / n o i t p i r c s e de g a k c a pr o d n e v 0 319 rp o p o nf 0 r 1 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 1 312 1 rk 1 . 5f 1 1 1 5 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 2 32 8 1 r , 4 1 rk 0 . 1f 1 0 0 1 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 3 317 1 r0 5 7f 0 0 5 7 3 0 6 0 w c r c % 1 m s3 0 6 0y a h s i v 4 33 4 u , 3 u , 1 u5 0 2 1 c sr e v i r d t e f l a u d8 - c i o sh c e t m e s 5 312 u4 3 4 2 c sr e l l o r t n o c e d o m t n e r r u c e s a h p - i r t d o o g r e w o p / w r o 0 2 - c i o s 0 2 - p o s s t h c e t m e s bill of materials - reference design (cont.) note 1: magnetic cool mu 77041, 5 turns awg #16 (800nh@0a, 600nh@25a) 15 ? 2005 semtech corp. www.semtech.com power management sc2434 applications information (cont.) efficency (%) 65.00 70.00 75.00 80.00 85.00 90.00 95.00 0 10203040506070 i_out(a) typical performance of the reference desig n the reference design implemented 1.5mohm output droop impedance as shown in fig. 9. fig. 9 - measured output drooping characteristics of the 60a design. the efficiency of the design is depends on the mosfet being used and thermal management requirements of controlling the pcb temperature and the mosfet junction temperature. the following efficiency curve is corresponding to 4mohm bottom fet, while the top fet has 12 mohm rdson. fig. 10 - typical efficiency curve for 12 mohm top fets and 4 ohm bottom fets. load line (vin=12v, vid=00100) 1.6 1.62 1.64 1.66 1.68 1.7 1.72 1.74 1.76 0 102030405060 i (a) vo(v) vo spec_h spec_l 16 ? 2005 semtech corp. www.semtech.com preliminary power management sc2434 applications information (cont.) the typical phase node voltage and the output voltage ripple waveform is shown in fig. 11 under 60a full load operation, where one can see the output ripple is very small and even with a frequency three times of the switching frequency. fig. 11 - the typical phase node voltage and the output voltage ripple waveform under 60a full load operation. the typical gate waveform for the top and bottom mosfets is also shown here, well-controlled dead time is demonstrated which ensures high efficiency operation of the vr. fig. 12 - the typical gate waveform for the top and bottom mosfets. ch2: hs gate ch3: phase node ch4: ls gate 17 ? 2005 semtech corp. www.semtech.com power management sc2434 applications information (cont.) the transient response for a maximum load step changes (10a to 60a) is shown in fig. 14, where one can see that accurate drooping will help to reduce the amount of output capacitance needed. please notice that using more multilayer ceramic capacitors for better high frequency decoupling can reduce the narrow voltage spikes. fig. 13 - transient response and the test condition: step load from 10a to 60a output capacitors: 14 units of 560uf oscon caps, 38 units of 10uf ceramic caps ch1: output voltage ch4: output current (1a = 27.5mv di/dt = 370a/us) meet intel p-4 spec output voltage load current 18 ? 2005 semtech corp. www.semtech.com preliminary power management sc2434 l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 20 .004 .169 .251 .173 .255 .007 - 20 0.10 0.65 bsc 6.40 bsc 4.40 6.50 - .177 .259 4.30 6.40 .012 0.19 4.50 6.60 0.30 bxn 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 1 3 2 n e1 bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view (.039) .004 .008 - .024 - - - - 0 .018 .003 .031 .002 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.05 .030 .007 .047 .042 .006 - (1.0) 0.60 - 0.75 0.20 - - - 1.20 1.05 0.15 a b c d e e/2 h plane d e a1 a2 a reference jedec std mo-153, variation ac. 4. inches b n ccc aaa bbb 01 e1 e l l1 e d c a2 a1 dim a min max millimeters min dimensions nom max nom outline drawing - tssop-20 land pattern - tssop-20 (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x inches dimensions z p y x dim c g millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. 19 ? 2005 semtech corp. www.semtech.com power management sc2434 this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. reference ipc-sm-782a, rlp no. 307a. 2. (.362) (9.20) z g y p (c) 7.00 .276 1.27 .050 0.60 .024 2.20 .087 11.40 .449 x inches dimensions z p y x dim c g millimeters 01 ccc aaa bbb max dimensions a1 e l n l1 h c e1 e d b a2 min dim a inches nom millimeters nom min max reference jedec std ms-013, variation ac. 4. e .041 .013 .104 .100 .012 2.35 - (1.04) - 1.04 0.33 - - - 2.65 2.55 0.30 .030 .010 - 0.75 0.25 - h h 3. dimensions "e1" and "d" do not include mold flash, protrusions or gate burrs. -b- controlling dimensions are in millimeters (angles in degrees). datums and to be determined at datum plane notes: 1. 2. -a- -h- side view a b c d e h e/2 bbb c a-b d see detail a l (l1) 0.25 plane gage c 01 (.041) .013 - .004 - - - - - 0 .016 .008 .081 .004 .093 8 0 0.33 0.10 - 8 0.40 0.20 2.05 0.10 .050 bsc .406 bsc 20 .010 .291 .295 .012 - 20 0.25 1.27 bsc 10.30 bsc 7.50 - .299 7.40 .020 0.31 7.60 0.51 .504 2x n/2 tips seating aaa c e/2 ccc c 2x 2 13 n a a2 a1 bxn d e1 .500 12.70 .508 12.80 12.90 plane detail a outline drawing - soic-20 land pattern - soic-20 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information |
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